1. Field of the Invention
The present invention relates to a differential signal generating circuit, and more particularly, to a differential signal generating circuit having a current spike suppressing circuit for suppressing a current spike generated at current change-over of a differential switch and reduce the power consumption.
2. Description of the Prior Art
Heretofore, a differential signal generating circuit 16 as shown in FIG. 8(a) has been known as a differential signal generating circuit for driving a high speed differential switch by means of a CMOS circuit. This differential signal generating circuit 16 is interposed between a D type flip-flop (referred to as DFF hereinafter) 17 for taking synchronism with data, and a differential switch 18 comprising p-channel MOS transistors MP3, MP4, and MP5. The differential signal generating circuit 16 receives a positive phase input IN and generates mutually opposing positive and negative phase signals OTP and OTN.
The differential signal generating circuit 16 formed by inverters 22-24, 32, 42, and 43 in multistages is used as shown in FIG. 9(a). In this circuit, specific output signals are obtained by connecting the inverters 22, 24, 32, and 43 so as to form even-numbered stages on the side of the positive phase output OTP, and by connecting the inverters 22, 23, and 42 so as to form odd-numbered stages on the side of the negative phase output OTN. Here, the sizes of the inverters are chosen, by taking the size of the inverters 22-24 unity, to be 2 for the inverter 32, and 3 for the inverters 42 and 43. In addition, the channel width W and the channel length L of the transistor MP3 are taken to be 250 .mu.m and 3 .mu.m, respectively, and the channel width W of the transistors MP4 and MP5 is set to be 60 .mu.m.
In order to obtain a differential switch operating at a higher speed, a DFF17A which generates a negative phase output ON as a data output in addition to the positive phase output Q, as shown in FIG. 8(b), may be used. A differential signal generating circuit 16A for using the negative phase output QN may be formed by inserting equivalent digital signal transmission circuits between the positive phase input IN and the positive phase output OTP, and between a negative phase input INN and the negative phase output OTN, respectively. For example, as shown in FIG. 9(b), the positive phase output OTP may be obtained by serially connecting the inverter 22 receiving the positive phase input IN and the inverter 42 driving the gate of the transistor MP4 of the differential switch 18, and the negative phase output OTN may be obtained by serially connecting the inverters 23 and 43.
The circuit of the DFF17 comprises p-channel MOS transistors MP31-MP34, n-channel MOS transistors MN31-MN34, and inverters 51, 52, 55, and 56, as shown in FIG. 10(a), forming a normally used CMOS D flip-flop. When a clock CK, positive relative to the level of a data signal input to a data input terminal D, changes from low level to high level (a clock with the level opposite to the positive phase clock CK is input to a negative phase clock terminal CKN), the DFF17 instantaneously fetches the signal level of data D and outputs the signal as a positive phase data Q. In the circuits in FIG. 10(a), and in FIG. 10(b) to be mentioned presently, the size of the inverters 51-52 is set to be 1.5, and that of the inverters 36 and 55-57 is set to be 0.75, by taking the size of the inverter 22 unity, and the channel width of the transistors is set to be 4 .mu.m.
In the DFF17A in FIG. 8(b), for the positive phase data output Q and the negative phase data output QN, the configuration is so arranged as to generate equivalent output signals by suppressing the increase in the number of elements. The circuit of the DFF17A is formed by adding a latch part consisting of inverters 36, 53, and 57, p-channel MOS transistors MP35 and MP36, and n-channel MOS transistors MN35 and MN36, to the output of the inverter 51, as shown in FIG. 10(b).
The differential switch 18 comprises a p-channel MOS transistor MP3 which is a constant current source, and p-channel MOS transistors MP4 and MP5 for switching the current. The transistors MP4 and MP5 are connected to the positive phase output OTP and the negative phase output OTN, respectively, of the differential signal generating circuit 16 so as to let a current flow in the transistor MP4 or MP5 to which is input the signal with the lower level of the two outputs.
In order to suppress the current spike at a current output terminal IO or ION through adjustment of the rise and fall times of the positive phase output OTP and the negative phase output OTN of the differential signal generating circuit 16 supplied to the differential switch 18, a circuit as shown in FIG. 9(c) is also employed. This circuit is disclosed in the Digest Paper No. 10.5, 1 entitled "A 350-MS/S 3.3-V 8-bit CMOS D/A Converter Using a Delayed Driving Scheme" of the 1995 Custom Integrated Circuits Conference (CICC).
The circuit in FIG. 9(c) uses similar component elements as in the circuit in FIG. 9(b), but the gate electrodes of p- and n-channel MOS transistors MP21, MP22 and MN21, MN22 are arranged to be driven by mutually different signals. Namely, the gate electrodes of the transistors MP21 and MP22 are connected to the outputs of the inverters 22 and 23, respectively, and the gate electrodes of the transistors MN21 and MN22 are connected to the inputs INN and IN, respectively, which are opposite in phase to the outputs of the transistors MN21 and MN22. As a result of such a connection, the signals of the p-channel MOS transistors MP21 and MP22 are delayed by an amount corresponding to one stage component of the inverter relative to the signals of the n-channel MOS transistors MN21 and MN22.
The circuit of the prior art differential signal generating circuits described above will be explained using the result of verification of transient analysis of the circuit operation by appropriately setting the sizes of respective transistors. What is meant by the size of the transistor is the channel width W, and the channel length L means the minimum producible length of the transistor. Further, the sizes of the inverters are set to be 2 for the inverter 32, 3 for the inverters 42 and 43, 1.5 for the inverters 51-53, and 0.75 for the inverters 36 and 55-57.
When the differential switch 18 in FIG. 8(a) is switched at a high frequency of several hundreds of MHz, sometimes there occur a nonconductive state, though momentarily, in the operation of the transistors MP4 and MP5, and as a result, a current spike is generated in the current output terminal IO or ION. This current spike has a drawback in that when the current path in either one of the transistors MP4 and MP5 is switched to the other current path, it prolongs the settling time before the current generated at the current output terminal IO or ION attain a stationary condition, obstructing the differential switching operation at high speed.
In other words, if the MOS transistors MP4 and MP5 are turned on simultaneously in the differential switch 18, the drain voltage of the transistor MP3 is raised and charge is accumulated in the portion connected to the drain. When either of the transistors MP4 or MP5 is turned off in this state, the accumulated charge is suddenly discharged and produces a spike at its output terminal IO or ION. Consequently, it takes time before the current settles stably in a stationary state, which gives rise to a problem that it obstructs the high speed operation of current switching of the differential switch.
The above problem will be described in more detail in the following.
First, the various transistors are set so as to give a normal threshold voltage which is 1/2 of a power supply voltage 3.3 V for the sizes of the inverters of the differential signal generating circuit 16 in FIG. 9(a). The result of verification of transient analysis when clocks and data as shown in FIGS. 11(a) and 11(b) are input for the combination of the circuit 16 having these inverters and the DFF17 in FIG. 10(a) as in FIG. 8(a), is shown by H of the positive phase output OTP and J of the negative phase output OTN in FIG. 12(a). From the figure it can be seen that the intersection P of the voltage waveforms at approximately the time 30 ns is about 2.8 V. In other words, since the gate potentials of both transistors MP4 and MP5 have values near the power supply voltage 3.3 V, both transistors are in states close to deenergized state, so a current spike L as shown in FIG. 14(a) is generated at the current output terminal IO.
The reason for this is the difference in the number of stages of the inverters in FIG. 9(a), namely, the positive phase output OTP side has one more stage of the inverter 24 than the OTN side, gaining more delay corresponding to this component, and tends to cause the voltage intersection P to be generated at a position closer to the power supply voltage side. That the gate voltages of the transistors of the differential switch are high means that the rise of the voltage waveforms is fast and their fall is slow. That is, owing to the fact that both transistors are of p-channel type, they are turned off soon if the rise is fast, and are turned on late if the fall is slow. In other words, both transistors are likely to be turned off simultaneously, and in the opposite case, the time for both transistors to remain turned on becomes long.
Even when the channel width W of the p-channel MOS transistor is made to be 14 .mu.m equal to the channel width W of the n-channel MOS transistor for the purpose of improving on this point, the intersection P of the positive and negative phase voltage outputs at 30 ns is reduced by only about 1.5 V, as shown in FIG. 12(b), and gives rise to a current spike L as indicated in FIG. 14(b).
Further, in order to reduce the size of the current spike L, a drive circuit may be configured as in FIG. 8(b) where the positive and negative phase signal paths are formed equivalently by using a DFF17A as in FIG. 10(b) for obtaining both of positive and negative phase outputs and a differential signal generating circuit 16A as shown in FIG. 9(b). In these circuits, the channel width W of each of the p- and n-channel MOS transistors in FIG. 9(b) is set to be 14 .mu.m in order to slow down the rise and hasten the fall of the inverters 22 and 23. This is arranged so as to make the three times the area of the inverter of reference size equal to the total sum of the gate areas of the MOS transistors. In addition, the values of W and L of the transistors in the other figures are set to be the same as before if their symbols are identical.
The simulation result of the verification of transient analysis using this circuit is shown in FIG. 13(a). Although the intersections R and P of the positive phase output OTP and the negative phase output OTN which arise at about the times 25 and 30 ns, respectively, show an improvement, the size of the current spike L at the current output terminal IO shown in FIG. 15(a) has a large value as in FIG. 14(b).
When the circuit in FIG. 9(c) instead of that in FIG. 9(b) is used as a mean for improving the current spike, the result of simulation of the transient analysis verification of the circuit where the channel width W of the p- and n-channel MOS transistors MP21, MP22 and MN21, MN22 is set to be 14 .mu.m is shown in FIG. 13(b). In this case, it is possible to reduce the waveform intersections R and P, where the positive and negative phase outputs OTP and OTN cross each other at about 25 and 30 ns, respectively, to about 0.5 V, and make the current spike L at the current output terminal IO small as in FIG. 15(b).
However, in this circuit the signals in the p-channel MOS transistors MP21 and MP22 are delayed than the signals in the n-channel MOS transistors MN21 and MN22 by the amounts corresponding to the inverters 22 and 23. Accordingly, when the gate input signals are inverted, there arises a state in which both of the p- and n-channel MOS transistors MP21, MP22 and MN21, MN22 find themselves in the energized state. Because of this, there is a problem in that the through current gets very large, and the number of elements of the DFF in FIG. 10(b) is increased, so that there are more defects than in the aforementioned circuit (the circuit in FIG. 8(a) using the circuits in FIG. 9(a) and FIG. 10(a)).
The simulation result of the transient analysis verification of these circuit is shown in FIGS. 16(a) and 16(b). Namely, for the circuit in FIG. 8(a) using the circuits in FIG. 9(a) and FIG. 10(a), the changes in the current consumption are represented by the peak current 3.95 mA and the mean current 238 .mu.A as shown in FIG. 16(a). For the circuit in FIG. 8(b) using the circuits in FIG. 9(c) and FIG. 10(b), the changes in the current consumption are represented by the peak current 6.11 mA and the mean current 354 .mu.A.